| Abstract: |
Electronic hardware engineering relies on artifacts such as schematics,
layouts, RTL blocks, firmware, simulation reports, timing results, board measurements, hardware-in-the-loop (HIL) traces, and outputs produced by agentic AI
systems. These artifacts support an engineering claim only when the evidence
behind them is valid for the configuration under review. In practice, evidence that
once passed may become stale after changes in design files, extracted views, package models, PDKs, tools, constraints, firmware, bitstreams, workloads, hardware
setups, HIL fixtures, review decisions, accepted-risk records, or tool-interface
policies.
This paper proposes ARTEMIX Verification-First, a closed-loop evidence-validity
framework for agentic electronic hardware engineering. Its central object is the
Evidence Validity Contract (EVC), which links an engineering claim to an artifact, verification method, result, validity boundary, invalidation triggers, review
state, decision state, accepted risk, and learning feedback. The framework defines
evidence debt, evidence gates, engineer-in-the-loop review, hardware-coupled
validation, responsibility separation, and learning-to-planning feedback.
HIL testing, FPGA-in-the-loop, emulation, and prototype execution are treated as
bounded evidence sources for claims that depend on timing, I/O behavior, physical
interaction, or system-level effects. Model Context Protocol (MCP)-compatible
interfaces are considered as one way to connect agents with tools and resources,
but tool invocation is not release permission, and release authority remains with
responsible engineers. ARTEMIX AI is used as an implementation architecture that
illustrates task contracts, evidence packets, claim ledgers, engine |